It is well known that components in integrated circuits (ICs), such as NMOS and PMOS transistors and interconnect structures, including contacts and vias, are shrinking with each new technology node, as articulated by Moore's Law. As structure sizes become smaller, it is more difficult to identify components with performance and reliability defects. In particular, a commonly used DC method of testing gates, contacts, vias, capacitors and interconnect isolation structures does not reliably identify all those structures with voids, contamination, or constricted regions that may cause failures during IC operation.